SDIO 2.0, SPI, UART 32-pin QFN package Integrated RF switch, balun, 24dBm PA, DCXO, and PMU Integrated RISC processor, on-chip memory and external memory interfaces Integrated MAC/baseband processors Quality of Service management I2S interface for high fidelity audio applications On-chip low-dropout linear regulators for all internal supplies Proprietary spurious-free clock generation architecture Integrated WEP, TKIP, AES, and WAPI engines Solutions Supports APSD for optimal VoIP applications Patented spurious noise cancellation algorithm for integration in SOC applications Supports Bluetooth co-existence interface Self-calibrated RF to ensure optimal performance under all operating conditions Zero factory tuning No external RF components Specifications 802.11 b/g/n Wi-Fi Direct (P2P), soft-AP Integrated TCP/IP protocol stack Integrated TR switch, balun, LNA, power amplifier and matching network Integrated PLLs, regulators, DCXO and power management units +19.5dBm output power in 802.11b mode Power down leakage current of Integrated low power 32-bit CPU could be used as application processor SDIO 1.1/2.0, SPI, UART STBC, 1¡Á1 MIMO, 2¡Á1 MIMO A-MPDU & A-MSDU aggregation & 0.4ms guard interval Wake up and transmit packets in Standby power consumption of
Trustpilot
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